FRDY=0, BVAL=0, BCLR=0
CFIFO Port Control Register
| DTLN | Receive Data Length.Indicates the length of the receive data. |
| FRDY | FIFO Port ReadyIndicates whether the FIFO port can be accessed. 0 (0): FIFO port access is disabled 1 (1): FIFO port access is enabled |
| BCLR | CPU Buffer Clear 0 (0): No operation 1 (1): Clear FIFO buffer on the CPU side. |
| BVAL | Buffer Memory Valid Flag 0 (0): Invalid 1 (1): Writing ended |